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22 a, rrio, cmos, 18 v operational amplifier data sheet ad8546 / ad8548 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011C2012 analog devices, inc. all rights reserved. features micropower at high voltage: 22 a maximum low input bias current: 20 pa maximum gain bandwidth product: 240 khz slew rate: 80 v/ms large signal voltage gain: 110 db minimum single-supply operation: 2.7 v to 18 v dual-supply operation: 1.35 v to 9 v unity-gain stable applications portable medical equipment remote sensors transimpedance amplifiers current monitors 4 ma to 20 ma loop drivers buffer/level shifting pin configurations out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ad8546 top view (not to scale) 09585-001 figure 1. ad8546 (8-lead msop) out a 1 ?in a 2 +in a 3 v+ 4 out d 14 ?in d 13 +in d 12 v? 11 +in b 5 +in c 10 ?in b 6 ?in c 9 out b 7 out c 8 ad8548 top view (not to scale) 09585-103 figure 2. ad8548 (14-lead soic_n) general description the ad8546 and ad8548 are dual and quad micropower, high input impedance amplifiers optimized for low power and wide operating supply voltage range applications. the ad8546 / ad8548 rail-to-rail input/output (rrio) feature provides increased dynamic range to drive low frequency data converters, making these amplifiers ideal for dc gain and buffering of sensor front ends or high impedance input sources used in wireless or remote sensors or transmitters. the low supply current specification (22 a) of the ad8546/ ad8548 over a wide operating voltage range of 2.7 v to 18 v or dual supplies (1.35 v to 9 v) makes these amplifiers useful for a variety of battery-powered, portable applications, such as ecgs, pulse monitors, glucose meters, smoke and fire detectors, vibration monitors, and backup battery sensors. the ad8546 / ad8548 are specified over the extended industrial temperature range of ?40c to +125c. the ad8546 is available in an 8-lead msop package; the ad8548 is available in a 14-lead soic_n package. table 1. micropower op amps 1 amplifier supply voltage 5 v 12 v to 18 v 36 v single ad8500 ad8663 ad8505 AD8541 ad8603 ada4505-1 dual ad8502 ad8546 op295 ad8506 ad8657 ada4062-2 ad8542 ad8667 ad8607 op281 ada4505-2 quad ad8504 ad8548 op495 ad8508 ad8669 ada4062-4 ad8544 op481 ad8609 ada4505-4 1 see www.analog.com for the latest selection of micropower op amps.
ad8546 /ad8548 data sheet rev. b | page 2 of 24 table of contents features .............................................................................................. 1 a pplications ....................................................................................... 1 pin configurations ........................................................................... 1 general description ......................................................................... 1 revisio n history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 18 v operation ............................. 3 electrical characteristics 10 v operation ............................. 4 electrical characteristics 2.7 v operation ............................ 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 typical performance characterist ics ..............................................7 applications information .............................................................. 17 input stage ................................................................................... 17 output stage ................................................................................ 18 rail - to - rail input and output .................................................. 18 resistive load ............................................................................. 18 comparator o peration .............................................................. 19 4 ma to 20 ma process control current loop transmitter .. 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 4/1 2 rev. a to rev. b added ad8548 and 14 - lead soic .................................. universal change s to product title , features section, general description section, and table 1 .................................................... 1 added f igure 2; renumbered figures sequentially ..................... 1 moved electrical characteristics 18 v operation section ...... 3 changes to table 2 ............................................................................ 3 changes to table 3 ............................................................................ 4 moved electrical characteristics 2.7 v operation section ..... 5 changes to table 4 ............................................................................ 5 changes to table 6 ............................................................................ 6 changes to f igure 4, figure 5 , figure 7, and figure 8 ................. 7 deleted figure 8 and figure 11 ....................................................... 8 changes to figure 9, figure 10, figure 12, and figure 13 ............ 8 changes to figure 2 2 and figure 2 5 ............................................ 10 changes to figure 3 3 ...................................................................... 12 changes to figure 63 and figure 64 ............................................ 18 updated outline dime nsions ....................................................... 21 added figure 7 2 ............................................................................. 21 changes to ordering guide .......................................................... 21 4/11 rev. 0 to rev. a changes to product title, features section, applications section, general description section , and table 1 ....................... 1 1/1 1 revision 0: initial version
data sheet ad8546/ad8548 rev. b | page 3 of 24 specifications electrical char acteristics 18 v operation v sy = 18 v, v cm = v sy /2 , t a = 25c, unless otherwise noted . table 2 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os v cm = 0 v to 18 v 3 mv v cm = 0.3 v to 17.7 v; ?40c t a +125c 7 mv v cm = 0 v to 18 v; ?40c t a +125c 12 mv offset voltage drift v os /t 3 v/c input bias current i b 5 2 0 pa ?40c t a +125c 2.6 na input offset current i os 4 0 pa ?40c t a +1 25c 5 .2 n a input voltage range ivr 0 18 v common - mode rejection ratio cmrr v cm = 0 v to 18 v 74 95 db v cm = 0.3 v to 17.7 v; ?40c t a +125c 68 db v cm = 0 v to 18 v; ?40c t a +125c 65 db large signal voltage gain a vo r l = 100 k? ; v o = 0.5 v to 17.5 v 110 1 25 db ?40c t a +125c 105 db input resistance r in 10 g? input capacitance differential mode c indm 3.5 pf common mode c incm 10.5 pf output characteristics output voltage high v oh r l = 100 k? t o v cm ; ?40c t a +125c 17.97 v output voltage low v ol r l = 100 k? to v cm ; ?40c t a +125c 30 mv short - circuit current i sc 12 ma closed - loop output impedance z out f = 1 khz ; a v = + 1 15 ? power supply power supply rejection ratio psrr v sy = 2.7 v to 18 v 95 1 15 db ?40c t a +125c 9 0 db supply current per amplifier i sy i o = 0 ma 18 22 a ?40c t a +125c 33 a dynamic performance slew rate sr r l = 1 m?; c l = 10 pf; a v = +1 80 v/ms settling time to 0.1 % t s v in = 1 v step ; r l = 100 k? ; c l = 10 pf 15 s gain bandwidth product gbp r l = 1 m?; c l = 10 pf; a v = +1 240 khz phase margin m r l = 1 m?; c l = 10 pf; a v = +1 60 degrees channel separation cs f = 10 khz ; r l = 1 m? 105 db noise performance voltage noise e n p - p f = 0.1 hz to 10 hz 5 v p - p voltage noise density e n f = 1 khz 5 0 nv/hz f = 10 khz 45 nv/hz current noise density i n f = 1 khz 0.1 pa/hz
ad8546 /ad8548 data sheet rev. b | page 4 of 24 electrical character istics 10 v operation v sy = 1 0 v, v cm = v sy /2 , t a = 25c, unless otherwise noted . table 3 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os v cm = 0 v to 10 v 3 mv v cm = 0.3 v to 9.7 v; ?40c t a +12 5c 8 mv v c m = 0 v to 10 v; ?40c t a +12 5c 12 mv offset voltage drift v os /t 3 v/c input bias current i b 2 15 pa ?40c t a +125c 2.6 na input offset current i os 3 0 pa ?40c t a +125c 5 .2 n a input voltage range ivr 0 10 v com mon - mode rejection ratio cmrr v cm = 0 v to 10 v 70 88 db v cm = 0 .3 v to 9.7 v; ?40c t a +12 5c 62 db v cm = 0 v to 10 v; ?40c t a +12 5c 60 db large signal voltage gain a vo r l = 100 k? ; v o = 0.5 v to 9.5 v 105 120 db ?40c t a +12 5c 100 db input resistance r in 10 g? input capacitance differential mode c indm 3.5 pf common mode c incm 3.5 pf output characteristics output voltage high v oh r l = 100 k? to v cm ; ?40c t a +125c 9.98 v output voltage low v ol r l = 100 k? to v cm ; ?40c t a +125c 2 0 mv short - circuit current i sc 11 ma closed - loop output impedance z out f = 1 khz ; a v = + 1 15 ? power supply power supply rejection ratio psrr v sy = 2.7 v to 18 v 95 115 db ?40c t a +12 5c 9 0 db supply current per amplifier i sy i o = 0 ma 18 22 a ?40c t a +125c 33 a dynamic performance slew rate sr r l = 1 m?; c l = 10 pf; a v = +1 75 v/ms settling time to 0.1% t s v in = 1 v step ; r l = 100 k? ; c l = 10 pf 15 s ga in bandwidth product gbp r l = 1 m?; c l = 10 pf; a v = +1 235 khz phase margin m r l = 1 m?; c l = 10 pf; a v = +1 6 0 degrees channel separation cs f = 10 khz ; r l = 1 m? 105 db noise performance voltage noise e n p - p f = 0.1 hz to 10 hz 5 v p -p voltage noise density e n f = 1 khz 5 0 nv/hz f = 10 khz 45 nv/hz current noise density i n f = 1 khz 0.1 pa/hz
data sheet ad8546/ad8548 rev. b | page 5 of 24 electrical character istics 2.7 v operation v sy = 2.7 v, v cm = v sy /2 , t a = 25c, unless otherwise noted . table 4 . parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os v cm = 0 v to 2.7 v 3 mv v cm = 0.3 v to 2.4 v; ?40c t a +125c 4 mv v cm = 0 v to 2.7 v; ?40c t a +125c 12 mv offs et voltage drift v os /t 3 v/c input bias current i b 1 10 pa ?40c t a +125c 2.6 na input offset current i os 20 pa ?40c t a +125c 5 .2 n a input voltage range ivr 0 2.7 v common - mode rejection ratio cmrr v cm = 0 v to 2.7 v 60 7 5 db v cm = 0.3 v to 2.4 v; ?40c t a +125c 58 db v cm = 0 v to 2.7 v; ?40c t a +125c 49 db large signal voltage gain a vo r l = 100 k? ; v o = 0.5 v to 2.2 v 9 7 1 1 5 db ?40c t a +125c 90 db input resistance r in 10 g? inpu t capacitance differential mode c indm 3.5 pf common mode c incm 3.5 pf output characteristics output voltage high v oh r l = 100 k? to v cm ; ?40c t a +125c 2.69 v output voltage low v ol r l = 100 k? to v cm ; ?40c t a +125c 10 mv short - circuit current i sc 4 ma closed - loop output impedance z out f = 1 khz ; a v = + 1 20 ? power supply power supply rejection ratio psrr v sy = 2.7 v to 18 v 9 5 1 15 db ?40c t a +125c 9 0 db supply current per amplifier i sy i o = 0 ma 18 22 a ?40c t a +125c 33 a dynamic performance slew rate sr r l = 1 m? ; c l = 10 pf ; a v = +1 50 v/ms settling time to 0.1% t s v in = 1 v step ; r l = 100 k? ; c l = 10 pf 20 s gain bandwidth product gbp r l = 1 m? ; c l = 10 pf ; a v = +1 1 9 0 khz phase margin m r l = 1 m? ; c l = 10 pf ; a v = +1 6 0 degrees channel separation cs f = 10 khz ; r l = 1 m? 105 db noise performance voltage noise e n p - p f = 0.1 hz to 10 hz 6 v p -p voltage noise density e n f = 1 khz 60 nv/hz f = 10 khz 56 nv/hz current noise density i n f = 1 khz 0.1 pa/hz
ad8546 /ad8548 data sheet rev. b | page 6 of 24 absolute maximum rat ings table 5 . parameter rating supply voltage 20.5 v input voltage (v?) ? 300 mv to (v+) + 300 mv input current 1 10 ma differen tial input voltage v sy output short - circuit duration to gnd indefinite storage temperature range ?65c to +150c operating temperature range ?40c to +125c junction temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c 1 th e input pins have clamp diodes to the power supply pins. limit t he input current to 10 ma or less whenever input signals exc eed the power supply rail by 0.3 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the dev ice. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended period s may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages using a standard 4 - layer board. table 6 . thermal resistan ce package type ja jc unit 8 - lead msop (rm-8) 142 45 c/w 14 - lead soic_n (r - 14) 115 36 c/w esd caution
data sheet ad8546/ad8548 rev. b | page 7 of 24 typical performance characteristics t a = 25c, unless otherwise noted. 0 5 10 15 20 25 30 35 40 ?2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?2.4 ?2.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 number of amplifiers v os (mv) 09585-002 v sy = 2.7v v cm = v sy /2 figure 3 . input offset voltage distri bution 0 10 20 30 40 50 60 70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 number of amplifiers tcv os ( v/c) v sy = 2.7v ?4 0 c t a +12 5 c 09585-004 figure 4 . input offset voltage drift distribution ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 v os (mv) v cm (v) v sy = 2.7v 09585-005 figure 5 . input offset voltage vs. common - mode voltage 0 5 10 15 20 25 30 35 40 ?2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?2.4 ?2.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 number of amplifiers v os (mv) 09585-105 v sy = 18v v cm = v sy /2 figure 6 . input offset voltage distribution 0 10 20 30 40 50 60 70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 number of amplifiers tcv os ( v/c) v sy = 18v ?4 0 c t a +12 5 c 09585-007 figure 7 . input offset voltage drift distribution ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 2 4 6 8 10 12 14 16 18 v os (mv) v cm (v) v sy = 18v 09585-008 figure 8 . input offset voltage vs. common - mode voltage
ad8546 /ad8548 data sheet rev. b | page 8 of 24 ?6 ?4 ?2 0 2 4 6 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 v os (mv) v cm (v) v sy = 2.7v C40c t a +125c 09585- 1 10 figure 9 . input offset voltage vs. common - mode voltage 0.1 1 10 100 1000 10000 25 50 75 100 125 i b (pa) temper a ture (c) | i b + | | i b ? | v sy = 2.7v 09585-010 figure 10 . input bias current vs. temperature ?4 ?3 ?2 ?1 0 1 2 3 4 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 i b (na) v cm (v) 25c 85c 125c v sy = 2.7v 09585-014 figure 11 . input bias current vs. common - mode voltage ?6 ?4 ?2 0 2 4 6 0 3 6 9 12 15 18 v os (mv) v cm (v) v sy = 18v C40c t a +125c 09585- 1 13 figure 12 . input offset voltage vs. common - mode voltage 0.1 1 10 100 1000 10000 25 50 75 100 125 i b (pa) temper a ture (c) v sy = 18v 09585-013 | i b + | | i b ? | figure 13 . input bias current vs. temperature 0 2 4 6 8 10 12 14 16 18 v cm (v) 25c 85c 125c v sy = 18v 09585-017 ?4 ?3 ?2 ?1 0 1 2 3 4 i b (na) figure 14 . input bias current vs. common - mode voltage
data sheet ad8546/ad8548 rev. b | page 9 of 24 0.01m 0.1m 1m 10m 100m 1 10 0.001 0.01 0.1 1 10 100 output vo lt age (v oh ) t o supp l y rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 2.7v 09585-015 figure 15 . output voltage (v oh ) to supply rail vs. load current 0.01m 0.1m 1m 10m 100m 1 10 0.001 0.01 0.1 1 10 100 output vo lt age (v ol ) t o supp l y rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 2.7v 09585-016 figure 16 . output voltage (v ol ) to supply rail vs. load current 2.695 2.696 2.697 2.698 2.699 2.700 ?50 ?25 0 25 50 75 100 125 output vo lt age, v oh (v) temper a ture (c) r l = 100k? r l = 1m? v sy = 2.7v 09585-020 figure 17 . output voltage (v oh ) vs. temperature 0.01m 0.1m 1m 10m 100m 1 10 output vo lt age (v oh ) t o supp l y rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 18v 0.001 0.01 0.1 1 10 100 09585-018 figure 18 . output voltage (v oh ) to supply rail vs. load current 0.01m 0.1m 1m 10m 100m 1 10 0.001 0.01 0.1 1 10 100 output vo lt age (v ol ) t o supp l y rai l (v) load current (ma) ?40c +25c +85c +125c v sy = 18v 09585-019 figure 19 . output voltage (v ol ) to supply rail vs. load current 17.975 17.980 17.985 17.990 17.995 18.000 ?50 ?25 0 25 50 75 100 125 output vo lt age, v oh (v) temper a ture (c) r l = 100k? r l = 1m? v sy = 18v 09585-023 figure 20 . output voltage (v oh ) vs. temperature
ad8546 /ad8548 data sheet rev. b | page 10 of 24 0 1 2 3 4 5 6 ?50 ?25 0 25 50 75 100 125 output vo lt age, v ol (mv) temper a ture (c) v sy = 2.7v 09585-021 r l = 100k? r l = 1m? figure 21 . output voltage (v ol ) vs. temperature 0 5 10 15 20 25 30 35 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 i sy per amp (a) v cm (v) ?40c +25c +85c +125c v sy = 2.7v 09585-123 figure 22 . su pply current per amplifier vs. common - mode voltage 0 5 10 15 20 25 30 35 0 3 6 9 12 15 18 i sy per am p (a) v sy (v) ?40c +25c +85c +125c 09585-026 figure 23 . supply current per amplifier vs. supply voltage 0 2 4 6 8 10 12 ?50 ?25 0 25 50 75 100 125 output vo lt age, v ol (mv) temper a ture (c) 09585-024 r l = 100k? r l = 1m? v sy = 18v figure 24 . output voltage (v ol ) vs. temperature 0 5 10 15 20 25 30 35 0 3 6 9 12 15 18 i sy per am p ( a) v cm (v) v sy = 18v ?40c +25c +85c +125c 09585-126 figure 25 . supply current per amplifier vs. common - mode voltage 0 10 20 30 40 50 60 ?50 ?25 0 25 50 75 100 125 i sy per am p (a) temper a ture (c) v sy = 2.7v v sy = 18v 09585-029 figure 26 . supply current per amplifier vs. temperature
data sheet ad8546/ad8548 rev. b | page 11 of 24 ?135 ?90 ?45 0 45 90 135 ?60 ?20 ?40 0 20 40 60 1k 10k 100k 1m phase (degrees) open-loo p gain (db) frequenc y (hz) phase gain 09585-027 c l = 10pf c l = 100pf v sy = 2.7v r l = 1m? figure 27 . open - loop gain and phase vs. frequency ?60 ?40 ?20 0 20 40 60 100 1k 10k 100k 1m closed-loo p gain (db) frequenc y (hz) v sy = 2.7v a v = +100 a v = +10 a v = +1 09585-028 figure 28 . closed - loop gain vs. frequency 1 10 100 1000 100 1k 10k 100k z out () frequenc y (hz) v sy = 2.7v a v = +1 a v = +10 a v = +100 09585-032 figure 29 . output impedance vs. frequency 1k 10k 100k 1m open-loo p gain (db) frequenc y (hz) 09585-030 phase ?135 ?90 ?45 0 45 90 135 ?60 ?20 ?40 0 20 40 60 gain phase (degrees) c l = 10pf c l = 100pf v sy = 18v r l = 1m? figure 30 . open - loo p gain and phase vs. frequency ?60 ?40 ?20 0 20 40 60 100 1k 10k 100k 1m closed-loo p gain (db) frequenc y (hz) v sy = 18v a v = +100 a v = +10 a v = +1 09585-031 figure 31 . closed - loop gain vs. frequency 1 10 100 1000 100 1k 10k 100k z out () frequenc y (hz) v sy = 18v 09585-035 a v = +1 a v = +10 a v = +100 figure 32 . output impedance vs. frequency
ad8546 /ad8548 data sheet rev. b | page 12 of 24 0 20 40 60 80 100 120 140 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) v sy = 2.7v v cm = v sy /2 09585-134 figure 33 . cmrr vs. frequency 0 20 40 60 80 100 100 1k 10k 100k 1m psrr (db) frequenc y (hz) psrr+ psrr? v sy = 2.7v 09585-034 figure 34 . psrr vs. frequency 0 10 20 30 40 50 60 70 10 100 1000 overshoot (%) ca p aci t ance (pf) 09585-038 v sy = 2.7v v in = 10mv p-p r l = 1m? os+ os? figure 35 . small signal overshoot vs. loa d capacitance 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) v sy = 18v v cm = v sy /2 0 20 40 60 80 100 120 140 09585-036 figure 36 . cmrr vs. frequency 0 20 40 60 80 100 100 1k 10k 100k 1m psrr (db) frequenc y (hz) psrr+ psrr? v sy = 18v 09585-037 figure 37 . psrr vs. frequency 0 10 20 30 40 50 60 70 10 100 1000 overshoot (%) ca p aci t ance (pf) os+ os? 09585-041 v sy = 18v v in = 10mv p-p r l = 1m? figure 38 . small signal overshoot vs. load capacitance
data sheet ad8546/ad8548 rev. b | page 13 of 24 time (100s/div) voltage (500mv/div) v sy = 1.35v a v = +1 r l = 1m? c l = 100pf 09585-039 figure 39 . large signal transient response time (100s/div) voltage (5mv/div) v sy = 1.35v a v = +1 r l = 1m? c l = 100pf 09585-040 figure 40 . small signal transient response time (40s/div) ?0.4 ?0.2 0 2 1 0 input voltage (v) output voltage (v) v sy = 1.35v a v = ?10 r l = 1m? input output 09585-044 figure 41 . positive overload recovery time (100s/div) voltage (5v/div) v sy = 9v a v = +1 r l = 1m? c l = 100pf 09585-042 figure 42 . large signal transient response time (100s/div) voltage (5mv/div) 09585-043 v sy = 9v a v = +1 r l = 1m? c l = 100pf figure 43 . small signal transient response time (40s/div) ?1 0 ?2 10 5 0 input voltage (v) output voltage (v) v sy = 9v a v = ?10 r l = 1m? input output 09585-047 figure 44 . positive overload recovery
ad8546 /ad8548 data sheet rev. b | page 14 of 24 time (40s/div) 0 0.2 0.4 0 ?1 ?2 input voltage (v) output voltage (v) v sy = 1.35v a v = ?10 r l = 1m? input output 09585-045 figure 45 . negative overload recovery time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy = 2.7v r l = 100k? c l = 10pf input output error band 09585-046 figure 46 . positive settling time to 0.1% time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy = 2.7v r l = 100k? c l = 10pf input output error band 09585-050 figure 47 . negative settling time to 0.1% time (40s/div) 0 1 2 0 ?5 ?10 input voltage (v) output voltage (v) v sy = 9v a v = ?10 r l = 1m? input output 09585-048 figure 48 . negative overload recovery time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy = 18v r l = 100k? c l = 10pf input output error band 09585-049 figure 49 . positive settling time to 0.1% time (10s/div) 0 +5mv ?5mv voltage (500mv/div) v sy = 18v r l = 100k? c l = 10pf input output error band 09585-053 figure 50 . negative settling time to 0.1%
data sheet ad8546/ad8548 rev. b | page 15 of 24 1 10 100 1000 10 100 1k 10k 100k 1m volt age noise densit y (nv/ hz) frequenc y (hz) v sy = 2.7v 09585-051 figure 51 . voltage noise density vs. frequency time (2s/div) voltage (2v/div) v sy = 2.7v 09585-052 figure 52 . 0.1 hz to 10 hz noise 0 0.5 1.0 1.5 2.0 2.5 3.0 10 100 1k 10k 100k 1m output swing (v) frequenc y (hz) 09585-056 v sy = 2.7v v in = 2.6v r l = 1m? a v = +1 figure 53 . output swing vs. frequency 1 10 100 1000 10 100 1k 10k 100k 1m volt age noise densit y (nv/ hz) frequenc y (hz) v sy = 18v 09585-054 figure 54 . voltage noise density vs. frequency time (2s/div) voltage (2v/div) v sy = 18v 09585-055 figure 55 . 0.1 hz to 10 hz noise 10 100 1k 10k 100k 1m output swing (v) frequenc y (hz) 0 2 4 6 8 10 12 14 16 18 20 09585-059 v sy = 18v v in = 17.9v r l = 1m? a v = +1 figure 56 . output swing vs. frequency
ad8546 /ad8548 data sheet rev. b | page 16 of 24 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequenc y (hz) 09585-057 v sy = 2.7v v in = 0.2v rms r l = 1m? a v = +1 figure 57 . thd + n vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k channe l se p ar a tion (db) frequenc y (hz) v in = 0.5v p-p v in = 1.5v p-p v in = 2.6v p-p 09585-058 r l 1m? 10k? v sy = 2.7v r l = 1m? a v = ?100 figu re 58 . channel separation vs. frequency 0.01 0.1 1 10 100 10 100 1k 10k 100k thd + n (%) frequenc y (hz) 09585-060 v sy = 18v v in = 0.5v rms r l = 1m? a v = +1 figure 59 . thd + n vs. frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k channe l se p ar a tion (db) frequenc y (hz) v in = 1v p-p v in = 5v p-p v in = 10v p-p v in = 15v p-p v in = 17v p-p 09585-061 r l 1m? 10k? v sy = 18v r l = 1m? a v = ?100 figure 60 . c hannel separation vs. frequency
data sheet ad8546/ad8548 rev. b | page 17 of 24 applications informa tion the ad8546 / ad8548 are low input bias current, micropower cmos amplifier s that operate over a wide supply voltage range of 2.7 v to 18 v. t h e ad8546 / ad8548 also employ unique input and output stages to achieve rail - to - rail input and output range s with very low supply current. input stage figure 61 shows the simplifie d schematic of the ad8546 / ad8548 . the input stage comprises two differential transistor pairs : an nmos pair (m1, m2) and a pmos pair (m3, m4). the input common - mode v oltage determines which differential pair turns on and is more active than the other . the pmos differential pair is active when the input voltage approaches and reaches the lower supply rail. the nmos differ - ential pair is needed for input voltages up to a nd including the upper supply rail. this topology allows the amplifier to maintain a wide dynamic input voltage range and maximize signal swing to both supply rails. for the greater part of the input common - mode voltage range, the pm os differential pair is active. differential pairs commonly exhibit different offset voltages. the handoff from one pair to the other creates a step - like char - acteristic that is visible in the v os vs. v cm graph s ( see figure 5 and figure 8 ). this characteristic is inherent in all rail - to - rail amplifiers that use the dual differential pair topology. therefore, always choose a common - mode voltage that does not include the region of handoff from one i nput differential pair to the other. additional steps in the v os vs. v cm graphs are also visible as the input common - mode voltage approaches the power supply rails. these changes are a result of the load transistors (m8, m9, m14, and m15) running out of he adroom. as the load transistors are forced into the triode region of operation, the mismatch of their drain impedances contributes to the offset voltage of the ampli - fier. this problem is exacerbated at high temperatures due to the decrease in the thresho ld voltage of the input transistors. see figure 9 and figure 12 for typical performance data. current source i1 drives the pmos transistor pair. as the input common - mode vo ltage approaches the upper rail, i1 is steered away from the pmos differential pair through the m5 transistor. the bias voltage, vb1, controls the po int where this transfer occurs. m5 diverts the tail current into a current mirror consisting of the m6 and m7 transistors. the output of the current mirror then drives the nmos transistor pair. note that the activation of this current mirror causes a slight increase in supply current at high common - mode voltages (see fig ure 22 and figure 25). the ad8546 / ad8548 achieve their high performance by using low voltage mos devices for their differen tial inputs. these low voltage mos devices offer excellent noise and bandwidth per unit of current. each differential input pair is protected by proprietary regulation circuitry (not shown in figure 61 ). the regula tion circuitry consists of a combination of active devices , which main - tain the proper voltages across the input pairs during normal operation , and passive clamping devices , which protect the amplifier during fast transients. however, these passive clampin g devices begin to forward - bias as the common - mode voltage approaches either power supply rail. this causes an increase in the input bias current (see figure 11 and figure 1 4 ). the input devices are a lso protected from large differential input voltages by clamp diodes (d1 and d2). these diodes are buffered from the inputs with two 10 k? resistors (r1 and r2). the differential diodes turn on when the differential input voltage exceeds approximately 600 mv; in this condition, the differential input resistance drops to 20 k?. v+ v? +in x r1 d1 d2 m1 m2 m7 m6 m3 m4 m5 vb1 m8 m10 m9 m16 m17 m1 1 vb2 out x m12 m14 m13 m15 i1 r2 ?in x 09585-062 figure 61 . simplified schematic
ad8546 /ad8548 data sheet rev. b | page 18 of 24 output stage the ad8546 / ad85 48 feature a complementary output stage consisting of the m16 and m17 transistors (see figure 61 ) . these transistors are configured in a class ab topology and are biased by the voltage source, vb2. this topology a llows the output voltage to go within millivolts of the supply rails, achieving a rail - to - rail output swing. the output voltage is limited by the output imped - ance of the transistors, which are low r on mos devices. the output voltage swing is a function of the load current and can be estimated using the output voltage to supply rail vs. load current graphs (see figure 15, figure 16, f igure 18 , and figure 19). rail - to - r ail input and output the ad8546 / ad8548 feature rail - to - rail input and output with a supp ly voltage from 2.7 v to 18 v. figure 62 shows the input and output waveforms of the ad8546 / ad8548 configured as a unity - gai n buffer with a supply voltage of 9 v and a resistive load of 1 m?. with an input voltage of 9 v, the ad8546 / ad8548 allow the output to swing very close to both rails. additionally, the ad8546 / ad8548 do not exhibit phase reversal. time (200s/div) voltage (5v/div) v sy = 9v r l = 1m? 09585-063 input output figure 62 . rail - to- rail input and output resistive l oad the feedback resistor alters the load resistance that an amplifier sees. t herefore, it is important to carefully select the value of the feedback resistors use d with the ad8546 / ad8548 . the amplifiers are capable of driv ing resistive loads down to 100 k?. the inverting op amp configuration section and the noni nverting op amp configuration section show how the feedback resistor changes the actual load r esistance seen at the output of the amplifier. inverting op amp configuration figure 63 shows the ad8546 / ad8548 in an invert ing config - uration with a resistive load, r l , at the output. the actual load seen by the amplifier is the parallel combination of the feedback resistor, r2, and the load, r l . for example, t he combination of a feedback resistor of 1 k? and a load of 1 m? results in an equivalent load resistance of 999 ? at the output. because the ad8546 / ad8548 are incapable of driving such a heavy load , performan ce degrades greatly. to avoid loading the output, use a larger feedback resistor, but consider the effect of resistor thermal noise on the overall circuit. ad8546/ ad8548 r1 r2 r l ?v sy r l, eff = r l || r2 +v sy v in v out 09585-064 figure 63 . inverting op amp configuration noni nverting op amp configurati on figure 64 shows the ad8546 / ad8548 in a noninverting config - uration with a resistive load, r l , at the output. the actual l oad seen by the amplifier is the parallel combination of r1 + r2 and r l . r1 r2 r l ?v sy r l, eff = r l || (r1 + r2) +v sy v in v out 09585-065 ad8546/ ad8548 figure 64 . noninverting op amp configuration
data sheet ad8546/ad8548 rev. b | page 19 of 24 comparator operation an op amp is designed to operate in a closed-loop configuration with feedback from its output to its inverting input. figure 65 shows the ad8546 configured as a voltage follower with an input voltage that is always kept at the midpoint of the power supplies. the same configuration is applied to the unused channel. a1 and a2 indicate the placement of ammeters to measure supply current. i sy + refers to the current flowing from the upper supply rail to the op amp, and i sy ? refers to the current owing from the op amp to the lower supply rail. ad8546 1/2 a1 100k ? 100k ? i sy + + v sy v out ?v sy i sy ? a2 09585-066 figure 65. voltage follower configuration as expected, figure 66 shows that in normal operating condition, the total current flowing into the op amp is equivalent to the total current flowing out of the op amp, where i sy + = i sy ? = 36 a for the ad8546 at v sy = 18 v. 0 5 10 15 20 25 30 35 40 024681012141618 i sy per du a l amplifier (a) v sy (v) i sy ? i sy + 09585-067 figure 66. supply current vs. supply voltage (voltage follower) in contrast to op amps, comparators are designed to work in an open-loop configuration and to drive logic circuits. although op amps are different from comparators, occasionally an unused section of a dual or quad op amp is used as a comparator to save board space and cost; however, this is not recommended. figure 67 and figure 68 show the ad8546 configured as a com- parator, with 100 k resistors in series with the input pins. the unused channel is configured as a buffer with the input voltage kept at the midpoint of the power supplies. ad8546 1/2 a1 100k ? 100k ? i sy + + v sy v out ?v sy i sy ? a2 09585-068 figure 67. comparator configuration a ad8546 1/2 a1 100k ? 100k ? i sy + + v sy v out ?v sy i sy ? a2 09585-069 figure 68. comparator configuration b the ad8546 / ad8548 have input devices that are protected from large differential input voltages by diode d1 and diode d2 (see figure 61). these diodes consist of substrate pnp bipolar transistors and turn on when the differential input voltage exceeds approximately 600 mv; however, these diodes also allow a current path from the input to the lower supply rail, resulting in an increase in the total supply current of the system. as shown in figure 69, both configurations yield the same result. at 18 v of power supply, i sy + remains at 36 a per dual amplifier, but i sy ? increases to 140 a in magnitude per dual amplifier. 0 20 40 60 80 100 120 140 160 024681012141618 i sy per du a lamplifier (a) v sy (v) i sy ? i sy + 09585-070 figure 69. supply current vs. supply voltage ( ad8546 as a comparator)
ad8546 /ad8548 data sheet rev. b | page 20 of 24 note that 100 k? resistors are u sed in series with the input of the op amp. if smaller resistor values are used, the supply current of the system increases much more. for more information about using op amps as comparators, see the an - 849 applic ation note , using op amps as comparators . 4 m a to 20 m a process control cu rrent loop transmitter a 2 - wire current transmitter i s often used in distributed control systems and process control applications to transmit analog signals between sensors and proc ess controllers. figure 70 shows a 4 ma to 20 ma current loop transmitter. r l 100? v dd 18v c2 10f c3 0.1f c1 390pf c4 0.1f r4 3.3k? q1 d1 4ma to 20ma r3 1.2k? r null 1m? 1% v ref r span 200k? 1% v in 0v to 5v r1 68k? 1% r2 2k? 1% notes 1. r1 + r2 = r. 1/2 ad8546 c5 10f r sense 100? 1% 09585-072 v out gnd adr125 v in figure 70 . 4 ma to 20 ma current loop transmitter the transmitter is powered directly from the control loop powe r supply, and the current in the loop carries signal from 4 ma to 20 ma. thus, 4 ma establishes the baseline current budget within which the circuit must operate. the ad8546 is an excellent choice due to its lo w supply current of 33 a per amplifier over temperature and supply voltage. the current transmitter controls the current flowing in the loop, where a zero - scale input signal is represented by 4 ma of current and a full - scale input signal is represented by 20 ma. the transmitter also floats from the control loop power supply, v dd , whereas signal ground is in the receiver. the loop current is measured at the load resistor, r l , at the receiver side. with a zero - scale input, a current of v ref /r null flows throu gh r?. this creates a current, i sense , that flows through the sense resistor, as determined by the following equation: i sense, min = ( v ref r ? )/( r null r sense ) with a full - scale input voltage, current flowing through r? is increased by the full - scale chang e in v in /r span . this creates an increase in the current flowing through the sense resistor. i sense, delta = ( full - scale change in v in r? )/( r span r sense ) therefore, i sense, max = i sense, min + i sense, delta when r? >> r sense , the current through the loa d resistor at the receiver side is almost equivalent to i sense . figure 70 shows a design for a full - scale input voltage of 5 v. at 0 v of input, the loop current is 3.5 ma, and at a full - scale input o f 5 v, t h e l o o p current is 21 ma. this allows software calibration to fine - tune the current loop to the 4 ma to 20 ma range. t ogether, t he ad8546 and the adr125 consume quiescent current of only 160 a, making 3.34 ma current available to power additional signal conditioning circuitry or to power a bridge circuit.
data sheet ad8546/ad8548 rev. b | page 21 of 24 outline dimensions compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 71 . 8 - lead mini small outline package [msop] (rm - 8) dimensio ns shown in millimeters controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equi v alents for reference on l y and are not appropri a te for use in design. compliant t o jedec s t andards ms-012-ab 060606- a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc sea ting plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarit y 0.10 8 0 45 figure 72 . 14 - lead standard small outline package [soic_n] narrow body (r - 14) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option branding ad8546armz ?40c to +125c 8 - lead mini small outline package [msop] rm - 8 a2v ad8546armz -rl ?40c to +125c 8 - lead mini small outline package [msop] rm - 8 a2v ad8546armz -r7 ?40c to +125c 8 - lead mini small outline package [msop] rm - 8 a2v ad854 8 arz ?40c to +125c 14- lead standard small outline package [ soic_n ] r -14 ad854 8 arz - rl ?40c to +125c 14- lead standard small outline package [ soic_n ] r -14 ad854 8 arz - r7 ?40c to +125c 14- lead standard small outline package [ soic_n ] r -14 1 z = rohs compliant part.
ad8546/ad8548 data sheet rev. b | page 22 of 24 notes
data sheet ad8546/ad8548 rev. b | page 23 of 24 not es
ad8546/ad8548 data sheet rev. b | page 24 of 24 notes ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09585 - 0- 4/ 12(b)

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